High-speed imaging devices (high-speed video cameras) used for taking consecutive images of high-speed phenomena, such as explosions, destructions, combustions, collisions or electric discharges, for only a short period of time, have been conventionally known (for example, see Non-Patent Document 1). Such high-speed imaging devices need to perform an ultrahigh-speed imaging operation at a level of one million frames per second or even higher. Accordingly, they use solid-state image sensors capable of high-speed operations, which have special structures different from conventional image sensors used in commonly used video cameras, digital cameras and similar devices.
Conventionally known solid-state image sensors suitable for the aforementioned applications include a charge-coupled device (CCD) type solid-state image sensor called the “in-situ storage image sensor” (which is disclosed in Patent Document 1 and other documents) and a metal-oxide semiconductor (MOS) type solid-state image sensor (which is disclosed in Patent Documents 2, 3 and other documents). The latter type, which has been proposed by some of the present inventors in order to solve various problems related to the former type, is a MOS-type solid-state image sensor having two spatially separated areas (pixel area and memory area), where the pixel area includes a two-dimensional array of picture elements (pixels) each of which includes a photodiode and the memory area includes a two-dimensional array of memory-array units each of which corresponds to one picture element and has a large number of memory cells (capacitors) for storing image signals.
In the solid-state image sensor disclosed in Patent Document 2, the total number of picture elements is the same as that of the memory-array units, and each picture element is connected to one memory-array unit by a separate column line. This structure allows all the signals in the picture elements to be simultaneously transferred from the picture elements to the memory-array units through the respective column lines. However, since this design requires the same number of column lines as that of the picture elements and hence a considerably large area for the wiring of the column lines on the sensor chip, it is difficult to increase the aperture ratio of the light-receiving section (photodiode).
In the solid-state image sensor disclosed in Patent Document 3, N picture elements are connected to N memory-array units by one common column line (where N is an integer equal to or greater than two). This design reduces the total number of column lines to one N-th of the total number of picture elements and therefore requires a smaller area for the wiring of the column lines, which is advantageous for increasing the aperture ratio of the light-receiving section. However, the transfer of pixel signals from the picture elements to the memory-array units through the column lines cannot be simultaneously performed on all the picture elements; the pixel signals held in N picture elements sharing one column line must be transferred to the memory-array units by a time-sharing control.
Unlike the commonly used solid-state image sensors having only one column line per one column of picture elements, the previously described high-speed MOS-type solid-state image sensor has a greater number of column lines, which is equal to the number of picture elements per one column or one N-th of the number of picture elements per one column. This is because commonly used solid-state image sensors operate at comparatively low frame rates and are allowed to use a sufficiently long period of time to read signals from the picture elements, whereas high-speed solid-state image sensors must completely read signals within an incomparably short period of time (within a range from a few nanoseconds to several tens of nanoseconds for a high-speed imaging of one million frames per second or higher), which requires a reading and storing operation including the steps of simultaneously reading signals at all the picture elements and subsequently writing the signals in the memory cells, or the steps of simultaneously reading signals at one N-th of all the picture elements and subsequently writing the signals in the memory cells.
Although various ideas for high-speed operations have been adopted, the previously described conventional MOS-type solid-state image sensor for high-speed imaging has the following problem.
In any of the solid-state image sensors for high-speed imaging described in Patent Documents 2 and 3, a source follower amplifier is provided inside each picture element so as to write a voltage signal from the picture element into a memory cell in the memory-array unit by driving a column line. The load-current sources for these source follower amplifiers are collectively arranged in a current-source area provided between the pixel area and the memory area. This design is primarily aimed at reducing the pixel size and effectively using the surface area of the sensor chip.
In the aforementioned solid-state image sensors for high-speed imaging, the column line, which constitutes a portion of the load to be driven, has a sub-micron width (e.g. 0.28 μm), while its length is considerably long, reaching up to several millimeters, due to the separation between the pixel area and the memory area. Accordingly, the column line has a considerably high parasitic resistance (e.g. approximately 1 kΩ for an aluminum line). Furthermore, the presence of a plurality of closely located column lines extending parallel to each other on the sensor chip causes a considerably high parasitic capacitance (e.g. 1 pF). To charge and discharge a load having such a high resistance and high capacitance within a short period of time (e.g. 20 ns), the bias current supplied to the source follower amplifier for driving the column line must be, for example, as high as 100 μA (this value is a mere example; the actual value depends on the size of the source follower amplifier).
In the case where the load-current source is separated from the picture element in the previously described manner, the bias current flows through the column line itself. As a result, a voltage drop occurs due to the aforementioned parasitic resistance, causing an offset voltage between the outlet end (connected to the load-current source) and the inlet end (connected to the picture element) of the column line. Since there is a significant difference in the distance to the current-source area between a picture element located near the center of the pixel area and a picture element located near the bottom end of the same area (i.e. in a region close to the current-source area), the pixel-signal voltages at these picture elements have different offset voltages. Furthermore, the presence of the high-resistance column line between the driving transistor of the source follower amplifier inside the picture element and the load-current source deteriorates the gain characteristics of the source follower amplifier. The extent of this deterioration in the gain characteristics also significantly varies depending on whether the picture element is located near the center of the pixel area or near the bottom end of the same area, causing the gain characteristics to vary among the picture elements.
A variation in the gain characteristics among the picture elements also results from the following reason: If the same number of load-current sources as that of the picture elements is provided on the small current-source area, the return paths of the bias current for the source follower amplifiers will be gathered in the small space of the current-source area. For example, the solid-state image sensors disclosed in Patent Documents 2 and 3 have the entire set of picture elements divided into two halves, with each half coupled with a different current-source area and a different memory area. If, for example, the total number of pixels is 400×256, a high electric current of 400×128×100 μA=5.12 A produced by one half of the picture elements will instantaneously rush into one current-source area.
An attempt to lower the resistance of the power wire on the low-voltage side by increasing the wire's width cannot completely decrease the resistance to zero. Thus, the voltage drop due to the wire always exists, causing a rise in the low-voltage side potential near the current-source area (which is normally at the ground potential). (For example, the rise is approximately 500 mV for a wiring resistance of 0.1Ω.) As a result, the gate bias voltage of the current-source transistor fluctuates, causing a change in the bias current which determines the operation point of the source follower amplifier inside each picture element, and thus constituting a destabilizing factor for the gain characteristics. For example, in a system having the low-voltage side power wires connected to the current-source area from both sides of the sensor chip, the aforementioned rise in the ground-side potential is greater in the central region of the chip than at both ends. This is also a major cause of the difference in the gain characteristics among the picture elements.